files_xilinx = \
	xilinx/glbl.v \
	xilinx/STARTUPE2.v \
	xilinx/XADC.v

vals_analog = design.txt

files_IPat = \
	../../2024_0110/IPat_JtagCont/IPat_JtagCont.v \
	../../2022_0080/IPat_Io/IPat_Io_Output3.v \

files_all = \
	$(files_xilinx) \
	$(files_IPat) \
	top.v \
	tb.v

all: wave.vcd

sim.o: $(files_all) $(vals_analog)
	iverilog $(files_all) -T typ -o sim.o

wave.vcd: sim.o
	vvp -l sim.log sim.o

clean:
	del sim.o wave.vcd